• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Photonic chip, field programmable photonic matrix and photonic integrated circuit. The present invention refers to a photonic chip made by the combination and interconnection of programmable photonic processing blocks with the same orientation, with all their longitudinal axes in parallel, implemented on a photonic chip that is capable of implementing one or multiple photonic circuits simultaneous with optical feedback paths and/or linear transformations of multiple ports, by the appropriate programming of its resources and the selection of its input and output ports. The invention also refers to a parallel programmable photonic matrix (P-FPPA) comprising at least one programmable circuit based on beam splitters with the same parallel orientation/tunable with an independent coupling and phase shift configuration and offset High performance phase and building blocks. (Machine-translation by Google Translate, not legally binding)
    公开号:ES2730448A1
    申请号:ES201930410
    申请日:2019-05-09
    公开日:2019-11-11
    发明作者:López Daniel Pérez；Francoy José Capmany；Prometheus Dasmahapatra
    申请人:Universidad Politecnica de Valencia；
    IPC主号:
    专利说明:

    [0001]
    [0002]
    [0003]
    [0004] OBJECT OF THE INVENTION
    [0005]
    [0006] The present invention refers to a photonic chip made by the combination and interconnection of programmable processing blocks, with the same orientation, with all their longitudinal axes in parallel, implemented on a photonic chip that is capable of implementing one or multiple photonic circuits simultaneous with optical feedback paths and / or multiport linear transformations through the appropriate programming of its resources and the selection of its input and output ports. The invention also refers to a parallel programmable field (in situ) photonic matrix (P-FPPA), which comprises at least one programmable circuit based on tuner beam splitters with the same orientation with a Independent phase shift coupling and configuration and high performance peripheral building blocks.
    [0007]
    [0008] BACKGROUND OF THE INVENTION
    [0009]
    [0010] Multifunctional programmable photonics (PMP) seeks to design common configurations of integrated optical hardware that can implement a wide variety of functionalities through proper programming. Several authors have covered theoretical papers that propose different principles of configurations and designs for programmable circuits based on cascading beam splitters or Mach-Zehnder interferometers ( Mach-Zehnder interferometers, MZIs). These proposals offer versatile hardware solutions to implement programmable circuits, but none of them define a complete architectural solution for a photonic device that can be programmed to implement simple, complex or simultaneous arbitrary circuits.
    [0011]
    [0012] Additionally, it has been proven that the combination of optical processing units with the ability to program / tune / select the power split ratio between their ports and the phase response has led to waveguide mesh arrangements with different topologies of Mesh and innovative versatility in terms of functionality. In particular, some of the proposed topologies allow feedback loops within the provisions that allow the formation of optical cavities, Sagnac type loops and more complex circuit topologies. However, the proposed architectures are based on the combination of tunable basic units (TBUs) that have different spatial / angular orientation of the component. This means that the longitudinal axes of the TBUs are not parallel to each other. For example, the square topology is based on the horizontal (0o-TBUs) and 90o-TBUs; the triangular topology is based on 0o-TBU, 60o-TBU and -60oTBUs; The hexagonal topology is based on 0o-TBUs, 30o-TBU, -30o-TBUs and this is maintained for uniform and non-uniform arbitrary topologies. This imposes several practical restrictions: first, the occupied surface area is relatively large for most of the proposed topologies, which limits the density of integration and therefore the scalability of the circuits. This fact is exacerbated for large TBUs. Second, some photonic components are sensitive to orientation due to their intrinsic material and manufacturing and the geometry properties of the waveguides. For example, some phase actuators require a certain orientation of the component, so that the physical realization of the device is possible and to achieve a reasonable tuning efficiency along with it. With the schemes currently available, only phase tuners that support an arbitrary orientation of the component can be used. Moreover, some TBUs use 3-dB couplers (directional couplers or multimode interferometers), which are also sensitive to orientation, limiting the overall performance of the circuit.
    [0013]
    [0014] DESCRIPTION OF THE INVENTION
    [0015]
    [0016] The object of the invention described herein solves the problems set forth above and allows the design of programmable waveguide mesh arrangements in which said processing components have the same spatial / angular orientation, that is, a configuration in which all TBUs are parallel to each other, thus providing a clear technical advantage over current approaches in terms of ease of manufacture, performance and occupied surface. This means that the longitudinal axis of each TBU has the same orientation.
    [0017]
    [0018] The object of the invention is based on the replication and interconnection of programmable photonic analog block units with the same orientation and reconfigurable interconnections preferably implemented by a photonic chip. These components provide the basic building blocks to implement Basic analog optical operations (reconfigurable optical power and power division in addition to an independent phase shift). In a very broad sense, reconfigurable processing can be considered, in the same way as programmable logic blocks (PLB), perform digital operations in electronic FPGA or configurable analog blocks (CBA), which perform analog operations in field-programmable electronic arrays analog (FPAA). Therefore, and in view of the foregoing, it can be seen that the object of the invention allows one or more simultaneous photonic circuits and / or multiport linear transformations by means of the appropriate programming of its resources, that is to say the corresponding analog programmable photonic block and selection of its input and output ports, while maintaining the same spatial / angular orientation in all analog programmable photonic blocks. Therefore, the essential contribution of the invention consists in the interconnection schemes that allow the designer to maintain the orientation of the PPAB.
    [0019]
    [0020] The object of the invention is described in the set of claims, included herein by reference.
    [0021]
    [0022] The proposal of photonic chip, field programmable photonic matrix (P-FPPA) with the same orientation of the present invention presents a series of advantages inherent in approximations with field programmable hardware, extended by the circuit topologies introduced by the invention. These include:
    [0023] • Shorter times for production and marketing.
    [0024] • Less development for the prototype and non-recurring engineering expenses.
    [0025] • Reduced financial risk when developing ideas and translating them into ASPIC ( Application specific photonic integrated circuits).
    [0026] • Multifunctional and multitasking operation.
    [0027] • Circuit optimization.
    [0028] • Regular schemes and reduced footprints.
    [0029] • Better performance and reproducibility of analog programmable photonic blocks.
    [0030] • Increased number of alternative circuit topologies not limited by geometric factors.
    [0031]
    [0032] The proposed photonic chip, field programmable photonic matrix (P-FPPA) with the same orientation of the present invention is suitable for the following applications:
    [0033] • Aerospace and Defense (Avionics, communications, secure solutions, space) • Automotive (High resolution video, Network of vehicles for image processing and connectivity, automotive information and leisure)
    [0034] • Data centers (Servers, routers, switches, gateway / gateway)
    [0035] • High performance computing (Servers, Super computers, SIGINT systems, high-end radars, high-end beam training systems, quantum computing, high-speed neural networks)
    [0036] • Integrated circuit design (ASPIC prototyping, Hardware emulation) • Cable or wireless communications (Optical transport networks, 5G network processing connectivity interfaces, Mobile backhaul network (English Mobile Backhaul))
    [0037] • Hardware Accelerators.
    [0038] • Deep and machine learning applications.
    [0039]
    [0040] DESCRIPTION OF THE DRAWINGS
    [0041]
    [0042] To complement the description that is being made and in order to help a better understanding of the characteristics of the invention, according to a preferred example of practical implementation thereof, a set of drawings is attached as an integral part of said description. where, for illustrative and non-limiting purposes, the following has been represented:
    [0043]
    [0044] Figure 1 shows some non-limiting examples of an example schematic diagram of the proposed photonic chip of the invention, wherein the illustration shows a detail of the interconnection of the coupling scheme of the internal signal of analog programmable photonic blocks with the same orientation or Basic units tuning (TBUs) and following a uniform pattern. (Above: distribution of conventional hexagonal uniform waveguide mesh according to the state of the art, Bottom: proposed model with the same orientation of the present invention).
    [0045]
    [0046] Figure 2 shows some non-limiting examples of an example schematic diagram of the proposed photonic chip of the invention, wherein the illustration shows a detail of the interconnection of the coupling model of the internal signal of analog programmable photonic blocks and following a pattern uniform. (Above: distribution of conventional square uniform waveguide mesh according to the state of the art, Below: model proposed with the same orientation of the present invention).
    [0047] Figure 3 shows some non-limiting examples of an example of a schematic diagram of the proposed photonic chip of the invention, where the illustration shows a detail of the interconnection of the coupling model of the internal signal of analog programmer photonic blocks and following a pattern uniform. (Above: distribution of conventional triangular uniform waveguide mesh according to the state of the art, Bottom: proposed model with the same orientation of the present invention.
    [0048]
    [0049] Figure 4 shows some non-limiting examples of an example schematic diagram of the proposed photonic chip of the invention, wherein the illustration shows a detail of the interconnection of the coupling model of the internal signal of analog programmable photonic blocks and following a pattern uniform.
    [0050]
    [0051] Figure 5 shows on the left side, the main stages involved in the flow of the design / configuration of a photonic chip of the present invention and on the right side, the hardware and software layers of the photonic chip and the expanded design that includes blocks of high performance.
    [0052]
    [0053] Figure 6 shows a simultaneous implementation of a ring cavity, a Mach-Zehnder interferometer and a 3x3 multi-port interferometer that uses a photonic chip design of the present invention where all processing units have the same orientation.
    [0054]
    [0055] Figure 7 shows an implementation of FPPA with high performance building blocks that provides wavelength multiplexing and demultiplexing tasks. The arrangement of processing units can be coupled to this block allowing processing on different channels and different wavelengths.
    [0056]
    [0057] PREFERRED EMBODIMENT OF THE INVENTION
    [0058]
    [0059] In a preferred embodiment of the object of the invention, a device is provided as shown in Figure 1 where a field programmable photonic matrix (P-FPPA) is seen comprising at least one, but preferably a large number of photonic blocks Analog programmers (PPAB) with the same orientation, implemented as a series of photonic waveguide elements developed on a photonic chip substrate. These blocks have programmable characteristics and can propagate light in both directions. It should be taken into account that the design in Figure 1 does not adopt any particular interconnection geometry and that the resulting design shown is only for the purpose of illustration. Although various configurations for PPBAs can be considered, the design with very basic 4-port PPBA units is illustrated here. The scheme of said PPABs with the same orientation and their interconnections are shown in the square of Figure 1 for a particular axis orientation and without internal coupling paths. In general, different options will be considered, where all PPAB blocks will remain in the same orientation. Figures 1-4 show some of the possible interconnection options. The function of the PPBAs is to provide independent power coupling ratios and phase adjustments, as explained below.
    [0060]
    [0061] The PPAB is a 2x2 photonic component capable of independently configuring a common tunable phase shift A PPAB and a tunable optical power division ratio K = sin2d (0 <= K <= 1) between its optical waveguide input fields and its output fields guide optical output waves.
    [0062]
    [0063] Figure 5 shows some examples of simple RPI PPAB programming that lead to very basic operations required in the processing of photonic signals. Many more are possible.
    [0064]
    [0065] Through proper programming and concatenation of successive processing blocks with the same orientation, the P-FPPA can implement complex autonomous and / or parallel photonic circuits and signal processing transformations by discretizing conventional optical processing circuits in RPI units and PPAB
    [0066]
    [0067] In particular, this concept is illustrated by three generic designs that are depicted in Figure 5, respectively.
    [0068]
    [0069] The field programmable photonic matrix (P-FPPA) in parallel according to the invention is an array of elements with the same orientation that can be interconnected according to user specifications and configured for a wide variety of applications. A P-FPPA combines the programmability of the most basic reconfigurable photonic integrated circuits into a scalable structure, which allows programmable circuits with a higher processing density. Therefore, the complexity of Processing comes from interconnectivity. In addition, it solves the problems related to previous waveguide meshes in which the interconnection topology was limited by the orientations resulting from the TBU. Our proposed invention solves various problems: first, the occupied surface area is considerably reduced, improving the density of integration and therefore the versatility of the circuits. Second, some photonic components are sensitive to orientation due to the intrinsic properties of the material and the geometry of the waveguides. For example, some phase actuators require some component orientation to maintain reasonable tuning efficiency. With current approaches, only phase change effects that support an arbitrary orientation of the component can be used. In addition, some TBUs employ 3-dB couplers (directional couplers or multimode interferometers), which are also sensitive to orientation, limiting overall circuit performance. With the proposed invention, both the processing performance and the reproducibility and reliability of the circuit are improved.
    [0070]
    [0071] The area on the left of Figure 6 shows the main stages of the design flow process, which is described below. The starting point for the design flow is the entry of the corresponding application configuration to be implemented. The specifications are then processed by an optimization procedure to improve the area and performance of the final circuit. The specifications are then transformed into a compatible circuit of FPPA processing blocks (technological mapping), optimizing attributes such as delay, performance or number of blocks.
    [0072]
    [0073] The technological mapping phase transforms the optimized network into a circuit consisting of a restricted set of circuit elements (P-FPPA processing blocks). This is done by selecting parts of the network that can each be implemented by one of the available basic circuit elements, and then specifying how these elements will be interconnected. This will determine the total number of processing blocks required for the specific implementation.
    [0074]
    [0075] Next, a decision about placement is continued, assigning each processing block to a specific location in the P-FPPA. At that time, global routing is done by choosing the processing units that will operate as optical access paths. In contrast to FPGAs, this structure does not physically difference between processing blocks and interconnection resources. Previously, the configurations of the processing blocks are chosen correspondingly and the performance calculation and design verification are performed. It can be done either physically by feeding all the necessary configuration data to the programming units to configure the final chip, or by using precise P-FPPA models. At each stage it is possible to execute an optimization process that could decide to reconfigure any of the previous stages.
    [0076]
    [0077] From the above description it can be seen that the P-FPPA involves not only the physical hardware of the photonic level and electronic control, but also consists of a software layer (see upper right part of Figure 5).
    [0078]
    [0079] The stages contained in the generic design flow can be performed automatically by the software layer, by the user, or a mixture of the two, depending on the autonomy and capabilities of the P-FPPA. In addition, a failure in any of the stages will require an iterative process until the specifications are successfully achieved. The additional parallel optimization process (mainly automatic auto-configuration), allows robust operation, autocorrect attributes, further improving the processing power of the physical device.
    [0080]
    [0081] Similar to modern FPGA families, FPPA can include high performance peripheral and internal blocks (HPB) to expand its capabilities to include higher-level functionality set on the chip. This is shown schematically in the lower right part of Figure 5. Having these functions in common embedded in the chip reduces the required area and provides these functions with increased performance compared to those built from primitives. Moreover, some of them are impossible to obtain in a discretized version of basic processing blocks. Examples of these include elements with high dispersion, spiral wave guide delay lines, generic modulation and photo-detection subsystems, optical amplifiers and source subsystems and high-performance filtering structures, to name a few.
    [0082]
    [0083] A special case of HPB is an interconnection of the arrangement of basic processing units with multiplexing / demultiplexing devices of the input / output wavelength, any of which can be spectrally cyclic or non-cyclic. As illustrated in Figure 7, it introduces another degree of flexibility, allowing the processing of multiple wavelengths. In addition, the system allows processing in different channels / spatial modes along with different channels / frequency modes.
    [0084]
    [0085] In addition, the P-FPPA can incorporate multiple and independent processing cores, which can be interconnected between them and high-performance building blocks to increase processing performance. These processing cores of the waveguide meshes can be integrated into the same substrate or can be integrated into different chips.
    [0086]
    [0087] EXAMPLES OF OPERATION
    [0088]
    [0089] Figure 6 provides some examples in which the FPPA of different types is programmed to emulate and simultaneously implement different photonic circuits. In each case, the figure includes the FPPA scheme with colored processing units according to the code defined above and the schematics of the implemented circuits.
    [0090]
    [0091] PHYSICAL IMPLEMENTATION
    [0092]
    [0093] The physical implementation of the P-FPPA device requires an integrated optical approach based on either a silicon photonic platform or hybrid / heterogeneous lll-V photon silicon platforms.
    [0094]
    [0095] As for the PPAB elements, the currently available photonic technology options are based on any phase tuning effect such as: MEMS systems, thermo-optical effects, electro-optical, optomechanical effects, electrocapacitive effects or non-volatile phase actuators. These actuators and / or phase shifters are integrated into any interferometric structure with more than two ports. Finally, as mentioned above, more complex FPPFA schemes can be designed by adjusting different interconnection schemes between the processing blocks with the same orientation, some examples are shown in the lower part of Figures 1-4.
    权利要求:
    Claims (25)
    [1]
    1. A photonic chip, comprising at least two analog programmable photonic blocks (PPABs), implemented through a photonic chip, characterized in that the at least two analog programmable photonic blocks (PPABs) have the same orientation and are parallel to each other. .
    [2]
    2. A photonic chip according to claim 1, wherein each of the at least two analog programmable photonic blocks (PPABs) comprises a longitudinal axis, wherein the longitudinal axes of the at least two analog programmable photonic blocks (PPABs) are parallel .
    [3]
    3. A photonic chip according to any of the preceding claims, wherein the analog programmable photonic block (PPAB) comprises at least two photonic waveguide elements.
    [4]
    4. A photonic chip according to claim 3, wherein the photonic waveguide element is configured to allow propagation in both directions.
    [5]
    5. A photonic chip according to claim 3, wherein the photonic waveguide element is configured to be programmable to adjust the optical path to the desired arrangement.
    [6]
    A photonic chip according to any one of the preceding claims, wherein the analog programmable photonic block (PPAB) comprises at least two input ports and at least two output ports and is described by at least one unit 2x2 rotation matrix of the Unitary special group with different phase relationships between its four components.
    [7]
    7. A photonic chip according to claim 6, wherein it is programmed to adjust an arbitrary optical power division ratio K (0 <= K <= 1) in addition to adjusting a common phase shift A PPAB between at least one input port and at least one exit port.
    [8]
    8. A photonic chip according to any of the preceding claims, wherein at least two analog programmable photonic blocks (PPABs) with the same orientation are configured by a series of guide elements photonic waves developed in a photonic chip.
    [9]
    9. A programmable photonic matrix comprising at least two photonic elements with the same orientation according to any of the preceding claims.
    [10]
    10. An integrated photonic circuit comprising programmable tunable couplers for the interconnection of at least two programmable photonic elements with the same orientation as defined in claim 9 which uses tunable programmable couplers as its primary element for configuring interferometric structures.
    [11]
    11. An integrated photonic circuit according to claim 10, wherein the programmable tunable couplers with the same orientation can be interconnected in such a way that they allow the configuration of optical cavities, optical loops, and interferometric structures of both direct feed and return feed They use tunable couplers with an additional phase configuration as their primitive element.
    [12]
    12. An integrated photonic circuit according to claim 10, wherein it is interconnected with high-performance building blocks configured to perform basic optical processing tasks such as: optical amplification, optical sources, electro-optical modulation, opto photo-detection -electronics, optical absorption, variable optical attenuators, non-linear processing elements and matrices of delay lines, optical wavelength, (de) spatial multiplexing, modal and polarization, optical routing.
    [13]
    13. An integrated photonic circuit according to claim 10, wherein it is interconnected with high-performance building blocks configured to multiplex / demultiplex the wavelength of spatial division of light, whether in a cyclic form or not cyclic
    [14]
    14. An integrated photonic circuit according to claim 10, further comprising primitive components with the same orientation, implemented by a non-resonant Mach-Zehnder interferometer.
    [15]
    15. An integrated photonic circuit according to claim 10, further comprising primitive components with the same orientation, implemented by a non-resonant Mach-Zehnder interferometer with two arms of equal length.
    [16]
    16. An integrated photonic circuit according to claim 10, further comprising primitive components with the same orientation, implemented by a resonant interferometer.
    [17]
    17. An integrated photonic circuit according to claim 10, further comprising primitive components with the same orientation, implemented by dual-acting directional coupler.
    [18]
    18. An integrated photonic circuit according to claim 10, further comprising primitive components with the same orientation with an arbitrary number of ports.
    [19]
    19. An integrated photonic circuit according to claim 10, further comprising primitive components with the same orientation, implemented in which the phase and amplitude tuners are based on: nano-electromechanical systems (NEMS), and micro- systems electromechanical (MEMS), thermo-optical effects, electro-optical, opto-mechanical effects, electro-absorption, electro-capacitive effects, electro-inductive effects, non-volatile memrisors or phase actuators.
    [20]
    20. An integrated photonic circuit according to claim 10, wherein the waveguide mesh arrangements with the same PPAB orientation are distributed in a uniform topology.
    [21]
    21. An integrated photonic circuit according to claim 10, wherein the waveguide mesh arrangements with the same PPAB orientation are distributed in a non-uniform topology.
    [22]
    22. An integrated photonic circuit according to claim 10, wherein the waveguide mesh arrangements with the same orientation of the PPAB interconnections maintain the same length between all nodes.
    [23]
    23. An integrated photonic circuit according to claim 10, wherein the waveguide mesh arrangements with the same orientation of the PPAB interconnections They maintain arbitrary lengths between all nodes.
    [24]
    24. An integrated photonic circuit according to claim 12, wherein at least two arrangements of waveguide meshes are interconnected between them, allowing a multi-stage or multi-core platform.
    [25]
    25. An integrated photonic circuit according to claim 12, wherein the waveguide mesh arrangement is connected to an electrical subsystem that drives the actuators or actuators / receivers on the chip, to an electrical subsystem that monitors readings and to a microprocessor which runs the optimization and configuration programs.
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    同族专利:
    公开号 | 公开日
    ES2730448B2|2020-03-19|
    WO2020225471A1|2020-11-12|
    CA3141681A1|2020-11-12|
    EP3968067A1|2022-03-16|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    ES2695323A1|2018-11-19|2019-01-03|Univ Valencia Politecnica|METHOD OF CONFIGURATION AND OPTIMIZATION OF PROGRAMMABLE PHOTONIC DEVICES BASED ON MALLED STRUCTURES OF INTEGRATED OPTICAL GUIDEWAYS |
    ES2694249B2|2018-10-31|2019-05-16|Univ Valencia Politecnica|FOTONIC DIRECTIONAL COUPLER WITH INDEPENDENT TUNING AND DEPASS FACTOR TUNING|
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    优先权:
    申请号 | 申请日 | 专利标题
    ES201930410A|ES2730448B2|2019-05-09|2019-05-09|PHOTONIC CHIP, PROGRAMMABLE PHOTONIC MATRIX BY FIELD AND INTEGRATED PHOTONIC CIRCUIT.|ES201930410A| ES2730448B2|2019-05-09|2019-05-09|PHOTONIC CHIP, PROGRAMMABLE PHOTONIC MATRIX BY FIELD AND INTEGRATED PHOTONIC CIRCUIT.|
    EP20742301.3A| EP3968067A1|2019-05-09|2020-05-11|Photonic chip, field-programmable photonic array and photonic integrated circuit|
    PCT/ES2020/070298| WO2020225471A1|2019-05-09|2020-05-11|Photonic chip, field-programmable photonic array and photonic integrated circuit|
    CA3141681A| CA3141681A1|2019-05-09|2020-05-11|Photonic chip, field programmable photonic array and photonic integrated circuit|
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